1. Field of Invention
The present invention relates to a ferroelectric memory. More particularly, the invention relates to a ferroelectric memory to store multiple values equal to or more than three values in a single memory cell.
2. Description of Related Art
A ferroelectric memory having a ferroelectric capacitor that is usable as a storage device has an operation speed as high as that of a DRAM, and is non-volatile like a FLASH memory. Due to such characteristics, the ferroelectric memory that is usable as a memory device may replace traditional memories.
A related art memory device (1T1C structure, such as the example shown in FIGS. 3(a) and 3(b)), like a DRAM, is configured such that a single memory cell is formed of a transistor and a capacitor made of a ferroelectric material to ensure memory retention, and another memory device (2T2C structure) is configured such that another combination of a transistor and a capacitor for reference is added to each memory cell. In view of high integration technology in the future, however, the 1T1C OR 2T2C structure has a limit. Accordingly, some approaches have been investigated to enhance the integration scale. One approach is to study smaller-sized memory devices. A ferroelectric memory (1C structure) can be provided in which a single memory cell is formed of one ferroelectric capacitor alone, and a ferroelectric memory (1T structure) can be provided in which a single memory cell is formed of one transistor alone, the gate electrode of which includes a ferroelectric capacitor, such that storage of the ferroelectric capacitor causes the transistor to be turned on or off. Another approach is to enhance the integration scale by providing a memory capacity of three or more values for each ferroelectric memory cell.
The related art also includes methods of attaining multi-value storage, including a method disclosed in Japanese Unexamined Patent Application Publication No. 8-180673 in which a plurality of ferroelectric capacitors having different threshold voltages are connected in parallel to form a memory cell such that capacitors with the reverse polarization direction among the ferroelectric capacitors are differentiated in number to attain multi-value storage, and a method disclosed in Japanese Unexamined Patent Application Publication No. 8-124378 in which a voltage applied to a ferroelectric memory cell is controlled to produce a third intermediate storage state different from the saturated positive and negative polarization states. However, in the former method, since a single memory cell includes a plurality of ferroelectric capacitors, the size of the memory cell increases as the magnitude of multiple values increases. In the latter method, since the applied voltage varies depending upon the value to be stored, the size of a peripheral circuit inevitably increases as the magnitude of multiple values increases.